1. Field of the Invention
This invention is related to the field of processors and, more particularly, memory management units in processors.
2. Description of the Related Art
Processors typically implement address translation. When address translation is enabled, fetch addresses and load/store addresses are effective or virtual addresses. The effective/virtual address is translated through the address translation mechanism to arrive at a physical address (or real address). The terms physical address and real address, as used herein, are intended to be synonymous. The physical/real address is the address actually used to address memory. An effective address is the address generated to fetch the instruction (also referred to as the program counter, or PC, of the instruction) or the address generated from the address operands of a load/store instruction. In some cases, the effective address is equal to the virtual address. In other cases, the virtual address is generated based on the effective address (e.g. translated from the effective address, or generated by applying some predetermined operation on the effective address). The virtual address is then translated to the physical address
Address translation is used for a variety of reasons. For example, address translation can be used to provide a larger effective or virtual address space than the amount of physical memory included in the computer system could support. A slower secondary storage (e.g. disk storage) can be used as a page swap storage to swap pages in and out of the memory as needed by the program(s) being executed. Additionally, address translation can be used in multitasking environments to protect one task's memory from access/update by another task, and to provide each task with its own address space independent of which physical pages are allocated to the task. If the overall memory usage of the tasks exceeds the memory size, page swapping can again be used to retain memory contents and provide access to the pages that are currently in use.
Page tables are typically provided in the system memory, and the page tables store the virtual to physical translation mappings. Accordingly, an address translation includes one or more memory accesses to read the translation from the page tables. In order to speed the translation mechanism, many processors implement translation lookaside buffers (TLBs). The TLBs are caches of recently used translations. Accordingly, like a cache miss, a miss in the TLB involves added latency to fetch the translation data from the page tables. In one case, a TLB is programmable with a virtual address range. In response to a translation request in the virtual address range, the TLB can provide the translation and can also prefetch the translation of the next virtual page into the TLB.